1. Field of the Invention
The present invention relates to a method of manufacturing a gate structure for a semiconductor memory device. More specifically the invention relates to a method for improving upon the electrical properties provided by an ONO intergate dielectric.
2. Discription of the Related Art
In conventional semiconductor memory devices an "ONO" dielectric film is used as an intergate having a stacking structure consisting of a silicon oxide film/a silicon nitride film/a silicon oxide film. The ONO structure provides good withstanding voltage and retention characteristic with a relatively thin film.
However, semiconductor device manufacturers are continually pressured to increase effective device densities in order to remain cost competitive. As the ONO dielectric film becomes thinner, pinholes and poor electrical qualities charateristic of nitride cause low breakdown voltages and leakage adversly affecting the reliability of the memory device.
Accordingly, a need exists for an intergate dielectric film for use in semiconductor memory devices that can provide higher withstanding voltage and retention characteristics as the film thickness is reduced.
The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,661,056 (Takeuchi) discloses oxynitride forme on the oxide layer of an NO and NON dielectric stacks.
U.S. Pat. No. 5,597,754 (Lou et al.), U.S. Pat. No. 5,427,967 (Sadjadi) and U.S. Pat. No. 5,665,620 (Nguyen) disclose methods to form ONO stacks.
U.S. Pat. No. 5,443,998 (Meyer) discloses a method of forming a chlorinated ONO stack.
U.S. Pat. No. 5,407,870 (Okada) discloses an oxynitride/oxide/oxynitride stack.